1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to a device for neutralizing an electronic circuit in the event of an anomaly in a clock signal.
2. Description of Related Art
In memory or microprocessor-type integrated circuits, a specified number of instructions (or micro-instructions) is executed during each period of the clock signal. For example, in an EEPROM, several clock periods are needed to perform one read or write cycle. The clock signal is generally generated by an external clock circuit. The duration of the high states (or pulses) of the clock signal and of the low states is fixed to ensure the proper operation of the electronic circuit. The minimum times for either of these states are generally specified in the specification of the circuit.
Sometimes the clock signal may have defects or anomalies corresponding to an excessively short duration of one of the states of the clock signal (i.e., the duration of the state in question is smaller than the corresponding minimum duration defined in the specification of the circuit). For example, a parasitic pulse may appear between two successive pulses of the clock signal. There are many causes for the presence of such anomalies in the clock signal. In particular, they may reveal a problem of electromagnetic compatibility. This deformation of the clock signal either interrupts the execution of the instruction currently being executed by the electronic circuit and stops the operation of this circuit, or generates the execution of a wrong instruction.